Examples
Two designs ship with the repository: a small streaming accelerator used by the tests and the docs, and a five-stage processor from the parser test suite.
Demo: streaming accelerator
Source: packages/web/samples/demo/demo.sv. A top with an input FIFO, a controller, a compute block (two instances of a processing-element module, an accumulator, a mux, an adder) and an output FIFO. It has buses, fanout (clock and reset), feedback (ready/valid back-pressure and the accumulator loop), constants and a struct-free, parser-friendly style.
Open it: automatic layout · with layout rules · with the conflicting rule file

demo.layout.yaml: datapath on one row with fixed gaps, controller above compute, a 640×420 frame for compute.
compute expanded in place; the fifo_data net is selected and the highlight continues into data_in inside the frame.
compute: the two PEs, the adder and mux, the always_ff register block, and feedback lanes below.
always_comb next-state block and an always_ff state register, with the 2-bit state bus drawn thicker.ProcBase: a five-stage TinyRV2 processor
Source: core/tests/examples/ProcBase.v and its dependencies, from a course processor lab. ProcBase.v carries the // verilens: top pragma, and ProcBase.layout.yaml next to it puts the control unit before and above the datapath, gives both a readable frame, orders the datapath ports, and pins the pipeline stage order inside dpath.
cd core/tests/examples
../../../verilens ProcBase.v ProcBaseDpath.v ProcBaseCtrl.v DropUnit.v ProcDpathAlu.v ProcDpathImmGen.v \
IntMulAlt.v Lookahead.v muxes.v arithmetic.v regfiles.v tinyrv2_encoding.v -l ProcBase.layout.yaml
Twelve files, 22 modules. Six vc_* library cells (queues, enable registers, trace modules) are not part of the examples and render as dashed black boxes. Open the generated page ↗

ctrl above and left of dpath, queues and the instruction drop unit around them, black boxes dashed.
dpath expanded in its 960×560 frame: fetch, decode, execute, memory and writeback left to right; the surrounding boxes have not moved.Things worth clicking: the inst_D bus from the datapath back to the controller (a feedback route), the multiplier instance three levels deep (dpath → multiplier → …), and the diagnostics drawer, which reports two multiply-driven nets caused by struct-field assigns in the original source.
Writing your own layout file
Start from automatic layout, open the Layout tab, and add rules one at a time. Required rules are for things that must hold (stage order, a block that must sit left of another); preferred rules are for taste (rows, something above something else). The DSL page has the full semantics and the demo rule file; core/tests/examples/ProcBase.layout.yaml is the larger example.