VeriLens is an interactive RTL schematic viewer. Point it at a Verilog or SystemVerilog project and get a zoomable, hierarchical schematic: modules as boxes you can expand in place, nets you can trace across module boundaries, and a small YAML file to say how things should be arranged.
Install → · Quick start · Examples · GitHub
Whole-project analysis
A C++ core lexes, parses and links every file you give it, resolves instances across files, and emits a structural JSON model. No regular-expression parsing.
Quick start →Expand without reflow
Each module gets a fixed frame. Clicking [+] renders its contents inside that frame; nothing around it moves, and the camera stays put.
Layout you can version
A small YAML DSL expresses leftOf, above, alignY, port order and frame sizes per module instance, with required and preferred strengths and clear diagnostics.
One command
./verilens rtl/ -l layout.yaml builds what is missing, parses your sources and opens a self-contained HTML file you can send to anyone.
Status
VeriLens is an early, working tool. The parser handles the structural subset of Verilog-2005 and common SystemVerilog (always_ff/always_comb, ANSI ports, parameters, generate regions, gate primitives). It is not a full SystemVerilog front end.